A reconfigurable semiconductor integrated circuit such as a field-programmable gate array (FPGA) may implement a desired function by programming circuit configuration information to the semiconductor integrated circuit.
A reconfigurable semiconductor integrated circuit has a configurable logic block (CLB) including a plurality of basic logic elements, a switch block (SB), a connection block (CB), and wires that mutually connect these blocks. The semiconductor integrated circuit having these elements may connect the CLB in a programmable manner and thereby has longer wire lengths than an application-specific integrated circuit (ASIC), resulting in larger wire capacitance. Therefore, the wires in the semiconductor integrated circuit consume more power.
As a power saving technology applied to the ASIC field, a charge recycling technique is available.
When, in a logic circuit, the value of a signal changes from 1 to 0, all charge stored in a wire capacitor is released. If the value of the wire capacitance and a power supply voltage are respectively denoted C and VDD, electric power consumed is represented as CVDD2/2. With a charge recycling technique, when stored charge is released, part of them is stored in another capacitor. The charge in the other capacitor is reused during a next change of the signal from 0 to 1 to reduce power consumption.
A clock resonance technique is available as a type of charge recycling technique. In the clock resonance technique, an inductor is added to a clock wire net; an LC resonant circuit is created according to the inductance of the inductor and the capacitance of a clock wire to produce resonance. Thus, charge is reused between the inductor and the clock wire capacitor, reducing electric power consumed in the clock wire net.
If the above conventional charge recycling technique is applied to a semiconductor integrated circuit, the circuit area becomes large. With a technique, for example, when stored charge is released during a discharge, part of the released charge is stored in another capacitor, so the addition of the other capacitor increases the circuit area accordingly. The clock resonance technique is also problematic in that the addition of the inductor increases the circuit area accordingly.
The following are reference documents:                [Document 1] Japanese Laid-open Patent Publication No. 2001-195163,        [Document 2] Japanese Laid-open Patent Publication No. 2011-250107,        [Document 3] S. Chan, K. Shepard, and P. Restle, “Uniform-Phase Uniform-Amplitude Resonant-Load Global Clock Distributions”, Solid-State Circuits, IEEE Journal of, vol. 40, no. 1, pp. 102-109, January 2005, and        [Document 4] L. McMurchie and C. Ebeling, “Pathfinder: A Negotiation-Based Performance-Driven Router for FPGAs”, in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., USA, 1995, pp. 111-117.        